In developing a program to be executed by a computer, software pipeline (which is also referred to as software pipelining or modulo scheduling) may optimize loop processing. The software pipeline is a compiler optimization method of performing instruction scheduling for loop processing to improve instruction level parallelism in a loop. A bottleneck of execution performance of a large-scale program is mainly the loop processing. Accordingly, it is significantly important to optimize loop processing by software pipeline.
In software pipeline, instruction scheduling is performed across loop iterations. According to the scheduling, processing for multiple loops is executed in parallel, and live ranges of registers used in the loops overlap each other. Accordingly, register renaming is performed using a compiler so as not to use the same register in the loops executed in parallel.
Instructions to be executed by a processor are stipulated based on an instruction set architecture (ISA). The ISA may include a single instruction multiple data (SIMD) extension instruction. The SIMD extension instruction enables one instruction to be applied to multiple pieces of data. The enhancement of such ISA may improve throughput of the processor.
As techniques of improving the throughput of the processor, a technique for enhancing an instruction set architecture for vectorization instruction, for example, has been in consideration. Further, another technique has also been in consideration which shortens processing time by reducing the number of accesses to a register file.
One example of the techniques for increasing the efficiency of processing executed by the processor is a technique for vectorization of a conditional loop. Further, there is also another technique for selectively storing data elements of two combined sources in a destination through execution of an alignment instruction.
The related techniques are disclosed in, for example, Japanese Laid-open Patent Publication Nos. 2001-147804, and 2012-128790, and Japanese National Publication of International Patent Application No. 2014-510352.